LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT syncFIFO
PORT(
clk : IN std_logic;
reset : IN std_logic;
din : IN std_logic_vector(3 downto 0);
dout : OUT std_logic_vector(3 downto 0);
rd : IN std_logic;
wr : IN std_logic;
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal din : std_logic_vector(3 downto 0) := (others => '0');
signal rd : std_logic := '0';
signal wr : std_logic := '0';
signal dout : std_logic_vector(3 downto 0);
signal full : std_logic;
signal empty : std_logic;
constant clk_period : time := 10ns;
BEGIN
uut: syncFIFO PORT MAP (
clk => clk,
reset => reset,
din => din,
dout => dout,
rd => rd,
wr => wr,
full => full,
empty => empty
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process
begin
wait for clk_period;
wait until (clk'event and clk='1');wait for 1ns;
reset<='1';
wait until (clk'event and clk='1');wait for 1ns;
reset<='0';
wr<='1';
rd<='0';
din<="0000";
for i in 0 to 10 loop
wait until (clk'event and clk='1');wait for 1ns;
din<=din+'1';
end loop;
wr<='0';
rd<='1';
for i in 0 to 10 loop
wait until (clk'event and clk='1');wait for 1ns;
end loop;
wr<='1';
rd<='0';
din<="0000";
for i in 0 to 10 loop
wait until (clk'event and clk='1');wait for 1ns;
din<=din+'1';
end loop;
wr<='0';
rd<='1';
for i in 0 to 10 loop
wait until (clk'event and clk='1');wait for 1ns;
end loop;
wr<='1';
rd<='1';
din<="0000";
for i in 0 to 20 loop
wait until (clk'event and clk='1');wait for 1ns;
din<=din+'1';
end loop;
wait;
end process;
END;